1. Field of the Invention
The present invention relates generally to semiconductor memory devices, and more particularly, to a negative voltage generator for a semiconductor memory device.
2. Description of the Related Art
A typical semiconductor memory devices utilizes an access transistor in each memory cell to store, read and refresh data in the cell. The refresh time of a memory cell is degraded by the leakage current of the access transistor. A negatively biased word line scheme has been devised to reduce this leakage current. A memory device employing a negative word line scheme applies a negative voltage Vbb or Vnn to the word lines of non-selected memory cells. This is also referred to as back biasing the word line.
FIG. 1 illustrates a prior art negative voltage generator which includes an oscillator 100, a negative charge pump 200 and a level detector 300. The generator of FIG. 1 has commonly been used to generate a negative voltage (Vbb) for reverse biasing the substrate of a semiconductor device, thereby reducing leakage current. Thus, it is often referred to as a substrate voltage generator. It generates a regulated negative voltage supply using a negative feedback operation. When Vbb increases due to substrate leakage current, the detector 300 enables the oscillator 100 which then drives the charge pump 200. The voltage of Vbb is driven more negative by the charge pump until the detector disables the oscillator.
FIG. 2 illustrates a typical prior art Vbb level detector 300. When Vbb increases due to substrate leakage current, the source-drain equivalent resistance of M2 (700) increases, thereby causing the voltage of Node A to rise. When node A reaches the trip point of inverter 900, the output signal OUT goes high and enables the oscillator 100 which then drives the negative charge pump 200 with a rectangular wave signal. The negative charge pump includes a capacitor 400 and two diodes DGND (500) and DSUB (600) which are arranged in a typical negative charge pumping configuration. When the rectangular signal is high, node B is clamped at one threshold voltage (Vth) above ground by DGND, while the other end of the capacitor 400 is charged to the positive supply voltage Vdd. Then, when the rectangular signal goes low, the capacitor pumps negative charge to Vbb through DSUB.
To implement a negatively biased word line scheme, the prior art negative voltage generator described above with reference to FIGS. 1 and 2 has also been utilized to provide the negative bias for the word lines. However, this prior art generator is not very well suited for driving negative word lines. The regulator shown in FIGS. 1 and 2 was originally intended to provide a small amount of current for reverse or back biasing a semiconductor substrate. A negative word line scheme, however, requires large current drive capability to discharge a word line from a boosted voltage of Vpp to the negative voltage of Vbb or Vnn during a word line precharge operation. These large discharge currents cause fluctuations in the negative voltage supply. The drive circuitry for a negative word line scheme places additional demands on the negative voltage generator because it consumes additional operating current from the negative voltage supply.
Another problem with the prior art negative voltage generator is that the voltage gain of the detector 300 is very low (˜0.1), so the response time is slow. This causes a long on/off delay time (˜1 us) which results in a large ripple component in the negative voltage Vbb as shown in FIG. 3. A further problem with the detector is that it is highly sensitive to process and temperature variations.